1. Field of the Invention
The present invention relates generally to the fabrication of semiconductor device structures. More particularly, the present invention relates to semiconductor device structures with capacitor containers, contact apertures, or other openings therein that have increased height-to-width ratios. Further, the present invention relates to methods of making semiconductor device structures having capacitor containers, contact apertures, or other openings therein with increased aspect ratios.
2. Background of the Related Art
In computer semiconductor devices, such as dynamic random access memory (DRAM) semiconductor device modules, the memory capacitors typically are formed inside containers, such as phosphosilicate glass (PSG), borosilicate glass (BSG), or borophosphosilicate glass (BPSG) containers, through etching techniques. An exemplary partially fabricated semiconductor device structure 10 is schematically illustrated in FIG. 1. A conductive plug 11 located between neighboring conductive structures 12, such as transistor gate stacks, forms electrical contact with an active device region 14 of a semiconductor substrate 16, e.g., a silicon (Si) wafer. A planarized insulating layer 18, such as a BPSG layer, surrounds the conductive structures 12. The conductive plug 11 is formed within an opening through the insulating layer 18. A structural layer 20 having a height, H, overlies the insulating layer 18 and may also be formed of BPSG or similar material. A capacitor container 22 having a width W is formed in the structural layer 20, generally by etching the structural layer 20 through a photomask (not shown). The capacitor container 22 is a generally cylindrical cavity formed contiguous with the conductive plug 11 (or an active device region 14 of the semiconductor substrate 16) and includes sidewalls 24 that extend to an opening in the insulating layer 18.
Typically, etching techniques include the depositing, masking and patterning of protective layers, such as photoresists (not shown), which act as templates and may be patterned to form photomasks (not shown) through which structures in the desired layer (e.g., structural layer 20) of a semiconductor device structure may be defined. Wet etch or dry etch techniques may be employed to define semiconductor device structures. In contrast with wet etch techniques, techniques involving dry etch, including, without limitation, glow-discharge sputtering, ion milling, reactive ion etching (RIE), reactive ion beam etching (RIBE), plasma etching, point plasma etching, magnetic ion etching, magnetically enhanced reactive ion etching, plasma enhanced reactive ion etching, electron cyclotron resonance and high-density plasma etching, are capable of etching in a substantially anisotropic fashion. This means that the target area of a substrate is etched primarily in a substantially vertical direction relative to the exposed, or active, surface of the substrate. Thus, such dry etch techniques are capable of defining structures with substantially vertical sidewalls. Consequently, such dry etch techniques are capable of accurately reproducing the features of a photomask. Due to a trend in semiconductor fabrication processes toward decreased dimensions of structures on semiconductor devices, dry etching is often desirable for defining structures upon semiconductor device substrates.
Concurrent with ever-decreasing die sizes, the width (or diameter) of capacitor containers must be reduced. However, DRAM capacitors of sufficient size to store and maintain the requisite amount of charge to permit the necessary refresh time must still be provided.
Accordingly, it has been proposed to fabricate capacitor containers of dielectric materials having higher dielectric constants than materials typically utilized. However, a change in material would cause a substantial interference with existing semiconductor manufacturing processes and, thus, such solution is undesirable.
As capacitance is a function of the surface area of the capacitor, tremendous efforts have been made in the semiconductor industry to maintain or increase the surface areas of capacitors, despite a decrease in the widths of capacitor containers. By increasing the surface area of the container, and thus an electrode associated therewith, capacitance charge may be maintained, or even increased, for a capacitor container having a reduced width. Typically, surface areas of capacitors are increased by the formation of an enhanced surface area layer, such as a hemispherical grain (HSG) polysilicon layer, on the interior surface of the capacitor container. The HSG polysilicon layer increases the surface area of the capacitor container due to the three-dimensional hemispherical configuration and convolutions of the silicon. While this technique creates a capacitor container with an increased surface area relative to a similarly sized capacitor container that is not lined with HSG polysilicon, surface area is still limited by the confines of the capacitor container structure. That is, an HSG polysilicon-lined capacitor container having a smaller width will have a lesser surface area than an HSG polysilicon-lined capacitor container having a larger width, assuming the two capacitor containers have a substantially equivalent height.
A further approach to enhancing the total surface areas of capacitor containers involves modifying the geometrical layout of the containers. However, the usefulness of this technique is similarly limited by the confines of the capacitor container in that a particular geometrical layout in a capacitor container having a smaller width will have a lesser surface area than a similar geometrical layout in a capacitor container having a larger width and a substantially equivalent height.
As surface area is a function not only of the width of the capacitor container but also of the height thereof, a decrease in width accompanied by a proportional increase in height theoretically would provide a capacitor container having identical surface area. However, there are limitations to forming a large height-to-width ratio using known etching techniques due to the limitations of selective etching. For instance, preservation of the surface underlying the etched layer may become compromised if the aspect ratio of the capacitor container is too great.
As shown in FIG. 1 and previously described, integrated circuits, such as DRAM semiconductor device structures, typically include conductive structures 12, such as transistor gates, formed on the surface 16a of the semiconductor substrate 16. In addition to capacitor containers 22, semiconductor device structures typically also include contact apertures (not shown) formed in the structural layer 20, generally by etching the structural layer 20. Like capacitor containers 22, contact apertures are typically cylindrical cavities formed contiguous with a conductive plug 11 (or an active device region 14 of the semiconductor substrate 16). Through these contact apertures, digit lines (not shown) can contact the source or drain regions (not shown) of the transistor formed in the semiconductor substrate 16, as desired.
As is apparent, if the height of a capacitor container 22 is increased to maintain the necessary capacitance, the height of the contact apertures (not shown) similarly must increase. However, due to reduced die sizes and increased feature densities, this height increase must occur without increasing the width (or diameter) of the contact aperture. However, as contact apertures typically are etched, formation of a large height-to-width ratio is limited by the limitations of selective etching, as previously described.
Based upon the above, the inventor has recognized that a semiconductor device structure and method for manufacturing such structure that has one or more capacitor containers, contact apertures, or other openings therein with increased height-to-width ratios over those which may be formed using conventional techniques would be desirable. Further, the inventor has recognized that a semiconductor device structure having one or more capacitor containers, contact apertures, or other openings therein with increased aspect ratios that is simple to manufacture and does not interfere significantly with existing manufacturing processes would be advantageous.
The present invention includes semiconductor device structures and methods of making such structures that include one or more etched openings therein with increased height-to-width ratios, or aspect ratios. The structures of the present invention are formed by successive layer deposition wherein etching is affected, generally in a step-wise fashion, as the height of the semiconductor device structure is increased.
The present invention further includes semiconductor device structures and methods of making such structures that include one or more capacitor containers, contact apertures, or other openings therein having increased aspect ratios. The semiconductor device structures are formed by stacking an interlayer or cover layer atop a first structural layer and, subsequently, stacking a second structural layer atop the cover layer. Stepwise etching of capacitor containers, contact apertures, or other openings in the first and second structural layers and the cover layer provides increased height-to-width ratios of the resultant capacitor containers, contact apertures, or other openings.
Further, the present invention includes semiconductor device structures and methods of making such structures in which capacitor containers, contact apertures, or other openings having increased aspect ratios are formed by deposition of a second structural layer directly atop an etched first structural layer. Process conditions of the material of the second structural layer may be adjusted such that substantial non-conformity and low step coverage are achieved. Subsequent etching of the second structural layer results in semiconductor device structures with one or more capacitor containers, contact apertures, or other openings therein that have increased height-to-width ratios relative to those which may be formed using currently known techniques.
Additionally, the present invention includes a method for self-aligning openings in substantially vertically stacked structural layers of a semiconductor device structure. Etching of the structural layers, generally in a stepwise fashion, may result in semiconductor device structures having openings therein with increased aspect ratios.
Additional aspects of the invention, together with the advantages and novel features pertaining thereto, will be set forth in the description which follows and will also become readily apparent to those of ordinary skill in the art upon examination of the following and from the practice of the invention.